Radiation Hardened CMOS Microchip Designed for Cancer Radiotherapy

With this 12.8-cm square chip, physicians will be able to diagnose cancer and see the impact of radiotherapy treatment far more precisely than ever before.

A consortium led by Nigel Allinson, a professor of image engineering at University of Lincoln (Lincoln, UK), created DynAMITe, the wafer-scale chip that is 200 times larger than the processing chips that lie at the core of current personal computers (PCs).

The images it generates will show, according to the researchers, very precisely the impact of radiation on tumors as well as aid the detection in the earliest stages. It is also very strong, being able to survive many years of exposure to radiation. Prof. Allinson, said, "DynAMITe was designed for medical imaging, in particular mammography and radiotherapy, so the individual pixels are much larger than those found in consumer digital cameras or mobile phones. As it will withstand exposure to very high levels of X-ray and other radiation, it will operate for many years in the adverse environment of cancer diagnosis and treatment instruments; and represents a major advance over the existing technology of amorphous silicon panels."

The project has been funded by the UK Engineering and Physical Sciences Research Council (Swindon, UK) and involves medical physicists at the Institute of Cancer Research (ICR; London, UK) and the Royal Marsden Hospital (London, UK), who are investigating potential applications for the technology.

"Our clinical work has given us an insight into areas in which the existing technology falls short, and we were very pleased the consortium was able to design a microchip that met our exact specifications for medical imaging," said Prof. Phil Evans from the ICR. "We are looking forward to investigating all the potential uses for this chip in cancer research and treatment."

DynAMITe (Dynamic range Adjustable for Medical Imaging Technology) is an active pixel sensor developed in 0.18 micron CMOS technology. It possesses 1280 x 1280 pixels on a 100-micron pitch coplanar with 2560 x 2560 pixels on a 50-micron pitch. The chip can be operated at frame rates up to 90 frames per second. The device is two-side buttable, meaning that arrays of 2 x 2 devices can be assembled, with minimal border loss, to provide an imaging area in excess of 25 cm square.

Related Links:
University of Lincoln
UK Engineering and Physical Sciences Research Council